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1 ? fn8127.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x5083 cpu supervisor with 8kbit spi eeprom this device combines four popular functions, power-on reset control, watchdog timer, supply voltage supervision, and block lock serial eeprom memo ry in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset active for a period of time. this allows the power supply and oscillator to stabilize before the processor can execute code. the watchdog timer provides an independent protection mechanism for microcontrollers. when the microcontroller fails to restart a timer within a selectable time out interval, the device activates the reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device?s low v cc detection circuitry protects the user?s system from low voltage conditions, resetting the system when v cc falls below the minimum v cc trip point. reset is asserted until v cc returns to the proper operating level and stabilizes. five industry standard v trip thresholds are available, however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine- tune the threshold for applicat ions requiring higher precision. pinouts 8 ld tssop 8 ld soic, 8 ld pdip features ?low v cc detection and reset assertion - four standard reset threshold voltages 4.63v, 4.38v, 2.93v, 2.63v - re-program low v cc reset threshold voltage using special programming sequence - reset signal valid to v cc = 1v ? selectable time out watchdog timer ? long battery life with low power consumption - <50a max standby current, watchdog on - <1a max standby current, watchdog off - <400a max active current during read ? 8kbits of eeprom ? save critical data with block lock ? memory - block lock first or last page, any 1/4 or lower 1/2 of eeprom array ? built-in inadvertent write protection - write enable latch - write protect pin ? spi interface - 3.3mhz clock rate ? minimize programming time - 16 byte page write mode - 5ms write cycle time (typical) ? spi modes (0,0 & 1,1) ? available packages - 8 ld tssop, 8 ld soic, 8 ld pdip ? pb-free plus anneal available (rohs compliant) applications ? communications equipment - routers, hubs, switches - set top boxes ? industrial systems - process control - intelligent instrumentation ? computer systems - desktop computers - network servers ? battery powered equipment sck si v ss wp v cc cs /wdi so 1 2 3 4 8 7 6 5 x5083 reset x5083 cs /wdi wp so 1 2 3 4 reset 8 7 6 5 v cc v ss sck si data sheet june 15, 2006
2 fn8127.3 june 15, 2006 typical application block diagram uc reset cs sck si so wp vcc vss reset spi vcc vss x5083 2.7-5.0v 10k watchdog timer command decode & control logic si so sck cs /wdi v cc por and low generation v trip + - reset (x5083) voltage reset protect logic 8kbits eeprom watchdog detector wp array status register transition reset reset & watchdog timebase x5083 standard v trip level suffix 4.63v (+/-2.5%) -4.5a 4.38v (+/-2.5%) -4.5 2.93v (+/-2.5%) -2.7a 2.63v (+/-2.5%) -2.7 see ?ordering information? on page 3 for more details for custom settings, call intersil. x5083
3 fn8127.3 june 15, 2006 ordering information part number reset (active low) part marking v cc range (v) v trip range temperature range (c) package pkg. dwg. # x5083p-4.5a x5083p al 4.5-5.5 4.5-4.75 0 to 70 8 ld pdip mdp0031 x5083pz-4.5a (note) x5083p zal 0 to 70 8 ld pdip* (pb-free) mdp0031 x5083pi-4.5a x5083p am -40 to 85 8 ld pdip mdp0031 x5083piz-4.5a (note) x5083p zam -40 to 85 8 ld pdip* (pb-free) mdp0031 x5083s8-4.5a x5083 al 0 to 70 8 ld soic mdp0027 x5083s8z-4.5a (note) x5083 zal 0 to 70 8 ld soic (pb-free) mdp0027 x5083s8i-4.5a* x5083 am -40 to 85 8 ld soic mdp0027 x5083s8iz-4.5a* (note) x5083 zam -40 to 85 8 ld soic (pb-free) mdp0027 x5083v8-4.5a 583 al 0 to 70 8 ld tssop m8.173 x5083v8z-4.5a (note) 583 zal 0 to 70 8 ld tssop (pb-free) m8.173 x5083v8i-4.5a 583 am -40 to 85 8 ld tssop m8.173 x5083v8iz-4.5a (note) 583 zam -40 to 85 8 ld tssop (pb-free) m8.173 x5083p x5083p 4.5-5.5 4.25-4.5 0 to 70 8 ld pdip mdp0031 x5083pz (note) x5083p z 0 to 70 8 ld pdip* (pb-free) mdp0031 x5083pi x5083p i -40 to 85 8 ld pdip mdp0031 x5083piz (note) x5083p zi -40 to 85 8 ld pdip* (pb-free) mdp0031 x5083si x5083 i -40 to 85 8 ld soic mdp0027 x5083s8 x5083 0 to 70 8 ld soic mdp0027 x5083s8z (note) x5083 z 0 to 70 8 ld soic (pb-free) mdp0027 x5083s8i* x5083 i -40 to 85 8 ld soic mdp0027 x5083s8iz* (note) x5083 zi -40 to 85 8 ld soic (pb-free) mdp0027 x5083v8 583 0 to 70 8 ld tssop m8.173 x5083v8z (note) 583 z 0 to 70 8 ld tssop (pb-free) m8.173 x5083v8i 583 i -40 to 85 8 ld tssop m8.173 x5083v8iz (note) 583 iz -40 to 85 8 ld tssop (pb-free) m8.173 x5083p-2.7a x5083p an 2.7-5.5 2.85-3.0 0 to 70 8 ld pdip mdp0031 x5083pz-2.7a (note) x5083p zan 0 to 70 8 ld pdip* (pb-free) mdp0031 x5083pi-2.7a x5083p ap -40 to 85 8 ld pdip mdp0031 x5083piz-2.7a (note) x5083p zap -40 to 85 8 ld pdip* (pb-free) mdp0031 x5083s8-2.7a x5083 an 0 to 70 8 ld soic mdp0027 x5083s8z-2.7a (note) x5083 zan 0 to 70 8 ld soic (pb-free) mdp0027 x5083s8i-2.7a x5083 ap -40 to 85 8 ld soic mdp0027 x5083s8iz-2.7a* (note) x5083 zap -40 to 85 8 ld soic (pb-free) mdp0027 x5083v8-2.7a 583 an 0 to 70 8 ld tssop m8.173 x5083v8z-2.7a (note) 583 zan 0 to 70 8 ld tssop (pb-free) m8.173 x5083v8i-2.7a 583 ap -40 to 85 8 ld tssop m8.173 x5083v8iz-2.7a (note) 583 zap -40 to 85 8 ld tssop (pb-free) m8.173 x5083
4 fn8127.3 june 15, 2006 pin description x5083p-2.7 x5083p f 2.7-5.5 2.55-2.7 0 to 70 8 ld pdip mdp0031 x5083pz-2.7 (note) x5083p zf 0 to 70 8 ld pdip* (pb-free) mdp0031 x5083pi-2.7 x5083p g -40 to 85 8 ld pdip mdp0031 x5083piz-2.7 (note) x5083p zg -40 to 85 8 ld pdip* (pb-free) mdp0031 x5083s8-2.7* x5083 f 0 to 70 8 ld soic mdp0027 x5083s8z-2.7* (note) x5083 zf 0 to 70 8 ld soic (pb-free) mdp0027 x5083s8i-2.7* x5083 g -40 to 85 8 ld soic mdp0027 x5083s8iz-2.7* (note) x5083 zg -40 to 85 8 ld soic (pb-free) mdp0027 x5083v8-2.7 583 f 0 to 70 8 ld tssop m8.173 x5083v8z-2.7 (note) 583 fz 0 to 70 8 ld tssop (pb-free) m8.173 x5083v8i-2.7 583g -40 to 85 8 ld tssop m8.173 x5083v8iz-2.7 (note) 583 gz -40 to 85 8 ld tssop (pb-free) m8.173 note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. *add "-t1" suffix for tape and reel. *pb-free pdips can be used for through hole wa ve solder processing only. they are not intended for use in reflow solder process ing applications. ordering information (continued) part number reset (active low) part marking v cc range (v) v trip range temperature range (c) package pkg. dwg. # pin (soic/ pdip) pin tssop name function 13cs /wdi chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvolatile write cycle is und erway, the device will be in the standby power mode. cs low enables the device, placing it in the active power mode. prior to the start of any operation after power-up, a high to low transition on cs is required. watchdog input. a high to low transition on the wdi pin restarts the watchdog timer. the absence of a high to low transition within the watchdog time out period results in reset going active. 24so serial output. so is a push/pull serial data outp ut pin. a read cycle shifts data out on this pin. the falling edge of the serial clock (sck) clocks the data out. 57si serial input. si is a serial data input pin. input all opcodes, byte addresses, and memory data on this pin. the rising edge of the serial clock (sck) latches the input data. send all opcodes (table 1), addresses and data msb first. 68sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or data bits pr esent on the si pin. the fa lling edge of sck changes th e data output on the so pin. 35wp write protect. when wp is low, nonvolatile write operations to t he memory are prohibited. this ?locks? the memory to protect it against inadvertent changes when wp is high, the device operates normally. 46v ss ground 82v cc supply voltage 7 1 reset reset output . reset is an active low, open drain output which goes active whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 250ms. reset goes active if the watchdog timer is enabled and cs remains either high or low longer than the selectable watchdog time out period. a falling edge of cs will reset the watchdog timer. reset goes active on power-up at about 1v and remains active for 250ms after the power supply stabilizes. x5083
5 fn8127.3 june 15, 2006 principles of operation power-on reset application of power to the x5083 activates a power-on reset circuit. this circuit goes low at 1v and pulls the reset pin active. this signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. reset active also blocks communicati on to the devic e through the spi interface. when v cc exceeds the device v trip value for 200ms (nominal) the ci rcuit releases reset , allowing the processor to begin executing code. while v cc < v trip communications to the device are inhibited. low voltage monitoring during operation, the x5083 monitors the v cc level and asserts reset if supply voltage falls below a preset minimum v trip . the reset signal prevents the microprocessor from operating in a power fail or brownout condition and terminates any spi communication in progress. the reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. when v cc falls below v trip , any communications in progress are terminated and communications are inhibited until v cc exceeds v trip for t purst . watchdog timer the watchdog timer circuit monitors the microprocessor activity by monitoring the wdi input. the microprocessor must toggle the cs /wdi pin periodically to prevent a reset signal. the cs /wdi pin must be toggled from high to low prior to the expiration of the watchdog time out period. the state of two nonvolatile control bits in the status register determine the watchdog timer period. the microprocessor can change these watchdog bits with no action taken by the microprocessor these bits remain unchanged, even after total power failure. v cc threshold reset procedure the x5083 is shipped with a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applications where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x5083 threshold may be adjusted. the procedure is described below, and uses the application of a high voltage control signal. setting the v trip voltage this procedure is used to set the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure will directly make the change. if the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold voltage to the v cc pin and tie the wp pin to the programming voltage v p . then send a wren command, followed by a write of data 00h to address 01h. cs going high on the write operation initiates the v trip programming sequence. bring wp low to complete the operation. note: this operation also writes 00h to array address 01h. resetting the v trip voltage this procedure is used to set the v trip to a ?native? voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is something less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the new v trip voltage, apply the desired v trip threshold voltage to the vcc pin and tie the wp pin to the programming voltage v p . then send a wren command, followed by a write of data 00h to address 03h. cs going high on the write operation initiates the v trip programming sequence. bring wp low to complete the operation. note: this operation also writes 00h to array address 03h. x5083
6 fn8127.3 june 15, 2006 01234567 sck si cs 06h 012345678910 20 21 22 23 16 bits 0001h 02h wp v p = 15-18v 00h wren write address data figure 1. set v trip level sequence (v cc = desired v trip value) 01234567 sck si cs 06h 012345678910 20 21 22 23 16 bits 0003h 02h wp v p = 15-18v 00h wren write address data figure 2. reset v trip level sequence (v cc > 3v. wp = 15-18v) 1 2 3 4 8 7 6 5 x5083 v trip adj. v p reset 4.7k si so cs sck c adjust run figure 3. sample v trip reset circuit x5083
7 fn8127.3 june 15, 2006 v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 50mv) execute sequence reset v trip new v cc applied = old v cc applied - error error ?emax ?emax < error < emax yes no error emax emax = maximum desired error figure 4. v trip programming sequence x5083
8 fn8127.3 june 15, 2006 spi serial memory the memory portion of the device is a cmos serial eeprom array with intersil?s block lo ck protection. the array is internally organized as x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. the device is designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the device monitors the bus and asserts reset output if the watchdog timer is enabled and there is no bus activity within the user selectable time out period or the supply voltage falls below a preset minimum v trip . the device contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low during the entire operation. all instructions (table 1), addresses and data are transferred msb first. data input on the si line is latched on the first rising edge of sck after cs goes low. data is output on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it again to resume operations where left off. write enable latch the device contains a write enab le latch. this latch must be set before a write operation is initiated. the wren instruction will set the latch and the wrdi instruction will reset the latch (figure 7). this latch is automatically reset upon a power-up condition and after the completion of a valid write cycle. status register the rdsr instruction provides a ccess to the status register. the status register may be read at any time, even during a write cycle. the status regist er is formatted as follows. block lock memory intersil?s block lock memory provides a flexible mechanism to store and lock system id and pa rametric information. there are seven distinct block lock memory areas within the array which vary in size from one page to as much as half of the entire array. these areas and associated address ranges are block locked by writing the appropriate two byte block lock instruction to the device as descr ibed in table 1 and figure 9. once a block lock instruction has been completed, that block lock setup is held in the nonvolatile status register until the next block lock instruction is issued. the sections of the memory array that are block locked can be read but not written until block lock is removed or changed. status register/block lock/wdt byte 765 4 3 210 0 0 0 wd1 wd0 bl2 bl1 bl0 table 1. instruction set and block lock protection byte definition instruction format instruction name and operation 0000 0110 wren: set the write enable latch (write enable operation) 0000 0100 wrdi: reset the write enable latch (write disable operation) 0000 0001 write status instruction?followed by: block lock/wdt byte: (see figure 1) 000wd 1 wd 2 000 --->no block lock: 00h-00h--->none of the array 000wd 1 wd 2 001 --->block lock q1: 0000h-00ffh--->lower quadrant (q1) 000wd 1 wd 2 010 --->block lock q2: 0100h-01ffh--->q2 000wd 1 wd 2 011 --->block lock q3: 0200h-02ffh--->q3 000wd 1 wd 2 100 --->block lock q4: 0300h-03ffh--->upper quadrant (q4) 000wd 1 wd 2 101 --->block lock h1: 0000h-01ffh--->lower half of the array (h1) 000wd 1 wd 2 110 --->block lock p0: 0000h-000fh--->lower page (p0) 000wd 1 wd 2 111 --->block lock pn: 03f0h-03ffh--->upper page (pn) 0000 0101 read status: reads status register & pr ovides write in progress status on so pin 0000 0010 write: write operation followed by address and data 0000 0011 read: read operation followed by address x5083
9 fn8127.3 june 15, 2006 watchdog timer the watchdog timer bits, wd0 and wd1, select the watchdog time out period. these nonvolatile bits are programmed with the wrsr instruction. a change to the watchdog timer, either setting a new time out period or turning it off or on, takes effect, following either the next command (read or write) or cycl ing the power to the device. the recommended procedure for changing the watch-dog timer settings is to do a wren , followed by a write status register command. then execute a soft-ware loop to read the status register until the msb of the status byte is zero. a valid alternative is to do a wren, followed by a write status register command. then wait 10ms and do a read status command. read sequence when reading from the eeprom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the device, followed by the 16-bit address. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read eeprom array sequence (figure 5). to read the status register, the cs line is first pulled low to select the device followed by the 8-bit rdsr instruction. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line. refer to the read status register sequence (figure 6). write sequence prior to any attempt to write data into the device, the ?write enable? latch (wel) must first be set by issuing the wren instruction (figure 7). cs is first taken low, then the wren instruction is clocked into the device. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the eeprom memory array, the user then issues the write instruction followed by the 16 bit address and then the data to be written. any unused address bits are specified to be ?0?s?. the write operation minimally takes 32 clocks. cs must go low and remain low for the duration of the operation. if the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the same page and overwrite any data that may have been previously written. for a write operation (byte or page write) to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed (figure 8). to write to the status regist er, the wrsr instruction is followed by the data to be written (figure 9). data bits 5, 6 and 7 must be ?0?. read status operation if there is not a nonvolatile writ e in progress, the read status instruction returns the block lock setting from the status register which contains the watchdog timer bits wd1, wd0, and the block lock bits idl2-idl0 (figure 6). the block lock bits define the block lock condition (table 1). the watchdog timer bits set the operation of the watchdog timer (table 2). the other bits are reserved and will return ?0? when read. see figure 6. during an internal nonvolatile write operaiton, the read status instruction returns a high on so in the first bit following the rdsr instruction (the msb). the remaining bits in the output status by te are undefined. repeated read status instructions return the msb as a ?1? until the nonvolatile write cycle is complete. when the nonvolatile write cycle is completed, the rdsr instruction returns a ?0? in the msb position with the remaining bits of the status register undefined. subsequent rdsr instructions return the status register contents. see figure 10. reset operation the reset output is designed to go low whenever v cc has dropped below the minimu m trip point and/or the watchdog timer has reached its programmable time out limit. the reset output is an open drain output and requires a pull up resistor. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and receive an instruction. ? so pin is high impedance. ? the write enable latch is reset. ? reset signal is active for t purst . table 2. watchdog timer definition status register bits watchdog time out (typical) wd1 wd0 0 0 1.4s 0 1 600ms 1 0 200ms 1 1 disabled (factory default) x5083
10 fn8127.3 june 15, 2006 data protection the following circuitry has been included to prevent inadvertent writes: ? a wren instruction must be issued to set the write enable latch. ?cs must come high at the proper clock count in order to start a nonvolatile write cycle. ? when v cc is below v trip , communications to the device are inhibited. 0123456789 cs sck si so high impedance read instruction (1 byte) byte address (2 byte) data out 1514 3210 20 21 22 23 24 25 26 27 28 29 30 76543210 figure 5. read operation sequence 01234567 cs sck si so read status instruction so = status reg when no nonvolatile write cycle ... ... ... b l 2 b l 1 b l 0 w d 0 w d 1 figure 6. read status operation sequence x5083
11 fn8127.3 june 15, 2006 01234567 cs si sck high impedance so instruction (1 byte) figure 7. wren/wrdi sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 654 321 0 figure 8. eeprom array write sequence 0123456789 cs sck si so high impedance instruction 10 11 12 13 14 15 data byte 65 4 32 10 w d 1 w d 0 b l 2 l 1 l 0 bb figure 9. status register write sequence x5083
12 fn8127.3 june 15, 2006 01234567 cs sck si so so msb high while in the nonvolatile write cycle 01234567 read status instruction read status instruction so msb still high indicates nonvolatile write cycle still in progress 01234567 cs sck si so 01234567 read status instruction read status instruction 1st detected so msb low indicates end of nonvolatile write cycle 43210 wd1 wd0 bl2 bl1 bl0 nonvolatile write in progress nonvolatile write ends figure 10. read nonvolatile write status x5083
13 fn8127.3 june 15, 2006 symbol table 012345 cs sck si instruction t wc non-volatile write operation 67 next wait t wc after a write for new operation, if not using polling procedure figure 11. end of nonvolatile write (no polling) waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x5083
14 fn8127.3 june 15, 2006 . absolute maximum ratings operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65c to 135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to 150c voltage on any pin with respect to v ss . . . . . . . . . . . . . -1.0v to 7v d.c. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300c temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to 85c v cc range -2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v blank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. dc electrical specifications (over the recommended operating conditi ons unless otherwise specified.) symbol parameter test conditions limits unit min typ max i cc1 v cc write current (active) sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open 5ma i cc2 v cc read current (active) sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open 0.4 ma i sb1 v cc standby current wdt = off cs = v cc , v in = v ss or v cc , v cc = 5.5v 1a i sb2 v cc standby current wdt = on cs = v cc , v in = v ss or v cc , v cc = 5.5v 50 a i sb3 v cc standby current wdt = on cs = v cc , v in = v ss or v cc , v cc = 3.6v 20 a i li input leakage current v in = v ss to v cc 0.1 10 a i lo output leakage current v out = v ss to v cc 0.1 10 a v il (note 1) input low voltage -0.5 v cc x 0.3 v v ih (note 1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc > 3.3v, i ol = 2.1ma 0.4 v v ol2 output low voltage 2v < v cc 3.3v, i ol = 1ma 0.4 v v ol3 output low voltage v cc 2v, i ol = 0.5ma 0.4 v v oh1 output high voltage v cc > 3.3v, i oh = -1.0ma v cc - 0.8 v v oh2 output high voltage 2v < v cc 3.3v, i oh = -0.4ma v cc - 0.4 v v oh3 output high voltage v cc 2v, i oh = -0.25ma v cc - 0.2 v v olrs reset output low voltage i ol = 1ma 0.4 v power-up timing symbol parameter min max unit t pur (note 2) power-up to read operation 1 ms t puw (note 2) power-up to write operation 5 ms capacitance t a = +25c, f = 1mhz, v cc = 5v symbol test max unit conditions c out (note 2) output capacitance (so, reset , reset) 8 pf v out = 0v c in (note 2) input capacitance (sck, si, cs , wp )6pfv in = 0v notes: 1. v il min. and v ih max. are for reference only and are not tested. 2. this parameter is periodically sampled and not 100% tested. x5083
15 fn8127.3 june 15, 2006 equivalent a.c. load circuit at 5v v cc 5v so 100pf 5v 3.3k ? reset 30pf 1.64k ? 1.64k ? output a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 ac electrical specifications (over recommended operating conditi ons, unless otherwise specified) symbol parameter 2.7v-5.5v unit min max data input timing f sck clock frequency 0 3.3 mhz t cyc cycle time 300 ns t lead cs lead time 150 ns t lag cs lag time 150 ns t wh clock high time 130 ns t wl clock low time 130 ns t su data setup time 20 ns t h data hold time 20 ns t ri (note 3) input rise time 2s t fi (note 3) input fall time 2s t cs cs deselect time 100 ns t wc (note 4) write cycle time 10 ms data output timing f sck clock frequency 0 3.3 mhz t dis output disable time 150 ns t v output valid from clock low 130 ns t ho output hold time 0 ns t ro (note 3) output rise time 50 ns t fo (note 3) output fall time 50 ns notes: 3. this parameter is periodically sampled and not 100% tested. 4. t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. x5083
16 fn8127.3 june 15, 2006 serial output timing serial input timing power-up and power-down timing sck cs so si msb out msb?1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance v cc t purst t purst t r t f t rpd reset 0 volts v trip v trip x5083
17 fn8127.3 june 15, 2006 cs vs. reset timing reset output timing symbol parameter min typ max unit v trip reset trip point voltage, x5083pt-4.5a (note 6) reset trip point voltage, x5083pt reset trip point voltage, x5083pt-2.7a reset trip point voltage, x5083pt-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.00 2.7 v t purst power-up reset time out 100 200 280 ms t rpd (note 5) v cc detect to reset/output 500 ns t f (note 5) v cc fall time 0.1 ns t r (note 5) v cc rise time 0.1 ns v rvalid reset valid v cc 1v notes: 5. this parameter is periodically sampled and not 100% tested. 6. pt = package/temperature cs t cst reset t wdo t rst t wdo t rst reset output timing symbol parameter min typ max unit t wdo watchdog time out period, wd1 = 1, wd0 = 1(default) wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 100 450 1 off 200 600 1.4 300 800 2 ms ms sec t cst cs pulse width to reset the watchdog 400 ns t rst reset time out 100 200 300 ms x5083
18 fn8127.3 june 15, 2006 v trip programming timing diagram sck si cs 0001h (set) v cc (v trip ) v pe t tsu t thd t vph t vps v p v trip t rp t vpo t pcs 02h 06h 0003h (reset) wren write addr. 00 data v trip programming parameters parameter description min max unit t vps v trip program enable voltage setup time 1 s t vph v trip program enable voltage hold time 1 s t pcs v trip programming cs inactive time 1 s t tsu v trip setup time 1s t thd v trip hold (stable) time 10 ms t wc v trip write cycle time 10 ms t vpo v trip program enable voltage off time (between successive adjustments) 0 s t rp v trip program recovery period (between successive adjustments) 10 ms v p programming voltage 15 18 v v tran v trip programmed voltage range 2.0 5.0 v v tv v trip program variation after programming (0-75c). (programmed at 25c) -25 +25 mv notes: 7. v trip programming parameters are periodically sampled and are not 100% tested. 8. for custom v trip settings, contact factory. x5083
19 fn8127.3 june 15, 2006 x5083 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
20 fn8127.3 june 15, 2006 x5083 plastic dual-in-line packages (pdip) notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the l eads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. mdp0031 plastic dual-in-line package symbol pdip8 pdip14 pdip16 pdip18 pdip20 tolerance notes a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. b 2/99 d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8127.3 june 15, 2006 x5083 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m8.173 8 lead thin shrink narrow body small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n8 87 0 o 8 o 0 o 8 o - rev. 1 12/00

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